The present disclosure relates generally to information handling systems, and more particularly to synchronizing processors when entering a system management mode.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system (IHS). An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in IHSs allow for IHSs to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Processors used in IHSs are generally provided having cache memory for storing information that is accessible by the processor. Using the cache memory is generally faster than an IHS's main memory. The cache memory is traditionally smaller and faster than the main memory and may be used to store the data that is most frequently used by the processor. Processors are being provided with larger and larger cache memory sizes. Some cache memories utilize multi-level caches (e.g., level 1 (L1), level 2 (L2), level 3 (L3) and the like). For example, some processors may have a 4 MB L2 cache or a 16 MB L3 cache. However, any number of levels and any size of cache memory may be used.
Processors may be provided to including multiple core processors in a single package. Some processor packages may operate more efficiently by operating as two “logical” processors to the host operating system, thereby allowing the operating system to schedule two threads or processes concurrently in a multi-processor system. In other words, in multiple core processors, one processor appears to the system to be multiple processors. This is generally known in the art as threading. In some processors, 4, 8, 16 and 32 processor threads may be enabled. However, in other processors, any number of processor threads may be enabled.
A problem arises when the multiple processors/threads are called to enter a system management mode (SMM) simultaneously as the result of a system management interrupt (SMI). An SMI is generally known in the art as a command to interrupt the processor or processors to perform an action. Some examples of triggers for an SMI are system temperature, memory errors, and input/output trap (e.g., writing to an I/O port), certain hardware/software events, universal serial bus (USB) events, and/or a variety of other events. As an example of an SMI, the system may need to handle an SMI for what is known in the art as demand based switching (DBS) or other similar systems for allowing the clock speed of the processor to be dynamically changed by software.
In DBS or other similar systems, all the processors (e.g., central processing units (CPUs), application processors (APs)) may be required to enter their SMI handler. A timeout value of 256 micro seconds in the processor entry synchronization timing loop of the SMI handler may prevent a processor from hanging when one or more processors cannot enter it's SMI handler. During processor initialization, for example, it is generally expected behavior that a processor times out waiting for all processors to enter their SMI handler. Also for runtime SMI operation, a timeout of 256 micro seconds is generally more than adequate for most SMI's. Certain types of processor instructions however can delay a CPU from entering it's SMI handler beyond this 256 micro second timeout. Processors with large cache sizes, as described above, can be delayed more than 400 micro seconds or longer depending upon cache size from entering SMI when executing certain instructions, such as, WBINVD instructions. WBINVD instructions are generally known in the art as instructions to write back and flush internal caches and/or instructions to initiate writing-back and flushing of external caches. For certain types of SMIs, such as a DBS SMI, where all processors must enter their SMI handler and check-in or sync with all processors in the system, a long delay for one or more processors entering SMI may result in a timeout in the SMI handlers of the other processors. These early processors may exit their SMI handler before other processors that are still executing WBINVD or similar types of instructions enter SMI. Because processors are generally required to be in SMI simultaneously, this may result in a system hang or other type of catastrophic failure.
Accordingly, it would be desirable to provide improved synchronization for processors when entering a system management mode, absent the disadvantages discussed above.